The present invention relates to a semiconductor integrated device that is mounted on mobile communication equipment and the like, and more particularly to a technology effective in reducing distortion of the transmitted/received signals.
Recently, mobile phones have been developing with various services implemented using data communication in addition to voice communication.
The typical frequency bands of the mobile phone in Europe are the GSM (Global System for Mobile Communicator) system in the 900 MHz band and the DCS (Digital Cellular System) in the 1.8 GHz band, while those in the United States are the PCS (Personal Communication Service) system in the 1.9 GHz band and the GSM system in the 850 MHz band. In addition, the W-CDMA system using the 2 GHz band is now added and the situation makes it essential for the mobile phone terminal to introduce multi-band/multi-mode capabilities.
Along with the introduction of such multi-band/multi-mode capabilities to the mobile phone, a compact and high-performance SPDT (Single-Pole Double-Throw) switch is required for transmit/receive switching, which can select complex high frequency signals.
The SPDT switch is mainly required to reduce higher harmonic distortion.
In order to achieve the reduction of higher harmonic distortion, for example, there is a technology where FETs (Field Effect Transistors) making up the SPDT switch are connected in a cascade configuration (see Patent Reference 1).
When electric power sent from a transmission circuit is transmitted to the side of an antenna through the SPDT switch, the FET, which is in the OFF state and connected to the side of a reception circuit and the antenna side, will not be turned ON because it is not affected by the power of the transmission circuit. Thus, the input power is output to the antenna without leaking to a receiving system, so that a low-loss switch can be realized.
Further, the RF (high frequency) voltage on the FET is dispersed due to the cascaded connection, so that the RF voltage per stage can be reduced. The gate-source capacitance (Cgs) and gate-drain capacitance (Cgd), which cause the harmonic distortion, and the RF voltage imposed on the ON-resistance are all reduced, so that the harmonic distortion can be reduced.
As a measure to further improve the harmonic distortion in the introduction of the multi-gate capability, there is a technology that employs a circuit where a potential supply wiring is provided at a midpoint between the gates of a dual-gate FET (see Patent Reference 2). This makes it possible to stabilize the midpoint potential. As a result, the harmonic distortion can be reduced.
As another measure to improve the harmonic distortion in the introduction of the multi-gate capability, there is a technology that suppresses the amount of potential reduction due to a leak current by changing the potential supply wiring at the midpoint between the gates of the dual-gate FET, thereby to improve the harmonic distortion (see Patent Reference 3).
Further, some of the common SPDT switches are provided with a booster circuit for further reducing the distortion, taking into account the circuit technologies of the above described Patent References 1 to 3.
This booster circuit is connected to the gates of FETs connected between the side of a transmission circuit and the side of an antenna, respectively. When one of the FETs is turned ON, the booster circuit takes a high frequency power from the FET, generates a boosted voltage (approx. 4.5 V) which is higher than a control voltage (approx. 2 V), and applies the boosted voltage to the gate of the FET.
Further, the boosted voltage is applied through the gate of the ON-state FET, to a drain (source) of another OFF-state FET. The gate of the OFF-state FET are at a reference potential VSS (0 V), so that the gate-to-source (drain) voltage Vgs (Vgd) of the FETs is a negative voltage (up to about minus 4.5 V).
Thus, the FET enters a deeper OFF state where the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd) both decrease, so that the harmonic distortion can be reduced.
Patent Reference 1: Japanese Unexamined Patent Publication No. Hei 8(1996)-70245
Patent Reference 2: Japanese Patent Application No. 2004-353715
Patent Reference 3: Japanese Patent Application No. 2005-181669